Research


Quantum computing [Sponsored by NSF Convergence Accelerator, ICDS/Huck Institute Seed Grants]

Research

Quantum computing can provide exponential speed-up over classical counterparts to solve certain class of combinatorial problems e.g., data analytics, material discovery and drug synthesis. However, the Noisy-Intermediate-Scale-Quantum (NISQ)-era quantum computers available in near-term suffer from noise e.g. T1 relaxation time, T2 dephasing time, gate errors (both single-qubit and multi-qubit) and readout error. These are also called qubit quality metrics. Crosstalk, qubit-to-qubit (Q2Q) variation and temporal variations in qubit quality metrics also exist. Quantum error correction imposes prohibitive overhead for NISQ computers that possess limited number of qubits. The computing power of the quantum computer is severely impeded without error correction. There is a strong need to develop resiliency techniques to advance quantum computing. Hybrid classical-quantum computing using shallow depth variational algorithms e.g., Quantum Approximate Optimization Algorithm (QAOA) and Variational Quantum Eigensolver (VQE) has been explored to compute approximate solutions in presence of noise. However, these algorithms are also subjected to noise. This project studies modeling of various noise sources and designs-space exploration for various optimization problems such as, maxcut, factorization and object detection. We are also investigating quantum machine learning for applications such as, drug discovery.

Current students:

Junde Li, Koustubh Phalak, Collin Beaudoin, Satwik Kundu, Suryansh Updahyay, Jeremie Pope, Debarshi Kundu

Graduated students:

Md. Mahabubul Alam, Aakarshitha Suresh, Abdullah-Ash Saki

Related publications

[BC2] Abdullah Ash- Saki, Mahabubul Alam and Swaroop Ghosh, “Quantum True Random Number Generator ”, In Design Automation of Quantum Computers, Springer, 2021 (in Press). Link
[BC1] Abdullah Ash- Saki, Mahabubul Alam, Junde Li, and Swaroop Ghosh, “Error-Tolerant Mapping for Quantum Computing ”, In Emerging Computing: From Devices to Systems, Springer, 2020 (in Press). Link
[J5] Mahabubul Alam and Swaroop Ghosh. "QNet: A Scalable and Noise-Resilient Quantum Neural Network Architecture for Noisy Intermediate-Scale Quantum Computers." Frontiers in Physics (2022): 702 Link
[J4] A. Saki, R. Topaloglu & Ghosh, S. “Shuttle-Exploiting Attacks and Their Defenses in Trapped-Ion Quantum Computers ”, IEEE Access, 2021. [Impact factor: 3.56] Link
[J3] J Li, R Topaloglu, S Ghosh, “Quantum generative models for small molecule drug discovery ”, IEEE Transactions on Quantum Engineering (TQE), 2021. [Impact factor: NA] Link
[J2] Phalak, K., A. Saki, M. Alam, R. Topaloglu & Ghosh, S. “Quantum PUF for Security and Trust in Quantum Computing ”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2021. Accepted. [Impact factor: 3.04] Link
[J1] A. Ash-Saki, Alam, Mahabubul, and S. Ghosh, “Experimental Characterization, Modeling, and Analysis of Crosstalk in a Quantum Computer”, IEEE Transactions on Quantum Engineering (TQE), 2020 (accepted). Link
[C33] Mahabubul Alam, Satwik Kundu, and Swaroop Ghosh. "Knowledge Distillation in Quantum Neural Network using Approximate Synthesis.", IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2023. Link
[C32] Collin Beaudoin, Satwik Kundu, Rasit Onur Topaloglu, and Swaroop Ghosh. "Quantum Machine Learning for Material Synthesis and Hardware Security.", IEEE International Conference On Computer Aided Design (ICCAD), 2022. Link
[C31] Koustubh Phalak, Mahabubul Alam, Abdullah Ash-Saki, Rasit Onur Topaloglu, and Swaroop Ghosh. "Optimization of Quantum Read-Only Memory Circuits.", IEEE International Conference on Computer Design (ICCD), 2022 Link
[C30] Satwik Kundu, and Swaroop Ghosh. "Security Aspects of Quantum Machine Learning: Opportunities, Threats and Defenses." In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI) 2022, pp. 463-468. 2022. Link
[C29] Suryansh Upadhyay, Abdullah Ash Saki, Rasit Onur Topaloglu, and Swaroop Ghosh. "A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum Computers." In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI) 2022, pp. 305-308. 2022. Link
[C28] Mehdi Sadi, Yi He, Yanjing Li, Mahabubul Alam, Satwik Kundu, Swaroop Ghosh, Javad Bahrami, and Naghmeh Karimi. "Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware." In 2022 IEEE 40th VLSI Test Symposium (VTS), pp. 1-12. IEEE, 2022. Link
[C27] Mahabubul Alam and Swaroop Ghosh, “DeepQMLP: A Scalable Quantum-Classical Hybrid Deep Neural Network Architecture for Classification ”, IEEE VLSI Design, 2022. [Acceptance Rate: NA%]  Link
[C26] Junde Li and Swaroop Ghosh, “Scalable Variational Quantum Circuits for Autoencoder-based Drug Discovery ”, IEEE Design, Automation and Test in Europe Conference (DATE), 2022. Link
[C25] Abdullah Ash- Saki, Rasit Onur Topaloglu and Swaroop Ghosh, “Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers ”, IEEE Design, Automation and Test in Europe Conference (DATE), 2022. Link
[C24] A. Suresh, A. Saki, M. Alam, R. Topaloglu and S. Ghosh, “A Quantum Circuit Obfuscation Methodology for Security and Privacy”, ACM Hardware and Architectural Support for Security and Privacy (HASP), 2021. Link
[C23] A. Saki, A. Suresh, R. Topaloglu and S. Ghosh, “Split Compilation for Security of Quantum Circuits”, IEEE International Conference On Computer Aided Design (ICCAD), 2021. Link
[C22] M. Alam, Kundu, S., R. Topaloglu and S. Ghosh, “(Special Session Paper) Quantum-Classical Hybrid Machine Learning for Image Classification”, IEEE International Conference On Computer Aided Design (ICCAD), 2021. Link
[C21] A. Ash-Saki, M. Alam, Phalak, K., A. Suresh, R. Topaloglu and S. Ghosh, “(Invited) A Survey and Tutorial on Security and Resilience of Quantum Computing”, IEEE European Test Symposium (ETS), 2021. Link
[C20] Amy Farris, Anna Kim, Junde Li and S. Ghosh, “Situating a Middle/High School Introduction to Quantum Computing in Advanced Quantum Drug Discovery Efforts”, Mid Atlantic American Society of Engineering Education (ASEE) Conference, 2021. Link
[C19] J. Li, Alam, Mahabubul, Congzhau Sha, Jian Wang, Nikolay Dokholyan and S. Ghosh, “(Invited) Drug Discovery Approaches using Quantum Machine Learning”, IEEE Design Automation Conference (DAC), 2021. Link
[C18] Phalak, K., A. Ash-Saki, M. Alam, R. Topaloglu and S. Ghosh, “A superposition based quantum PUF for authentication of quantum computers”, Govt Microcircuit Applications and Critical Technology (GOMACTECH), 2021. Link
[C17] Alam, Mahabubul, A. Ash-Saki, J. Li and S. Ghosh, “(Invited) Impact of Noise on the Resilience and the Security of Quantum Computing”, IEEE International Symposium on Quality Electronic Design (ISQED), 2021. Link
[C16] Alam, Mahabubul, A. Ash-Saki, J. Li and S. Ghosh, “(Special Session Invited Paper) Noise Resilient Compilation Policies for Quantum Approximate Optimization Algorithm”, IEEE International Conference on Computer Aided Design (ICCAD), 2020. [Acceptance Rate: 19%] Link
[C15] Alam, Mahabubul, A. Ash-Saki, and S. Ghosh, “Circuit Compilation Methodologies for Quantum Approximate Optimization Algorithm”, IEEE International Conference on Microarchitecture (MICRO), 2020. [Acceptance Rate: 19%] Link
[C14] Li, J., and S. Ghosh, “Quantum-soft QUBO Suppression for Accurate Object Detection”, IEEE European Conference on Computer Vision (ECCV), 2020. [Acceptance Rate: 27%] Link
[C13] A. Ash-Saki, Alam, Mahabubul, and S. Ghosh, “Analysis of crosstalk in NISQ devices and security implications in multi-programming regime”, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020. [Acceptance Rate: 25%] Link
[C12] Qiu, L., M. Alam, A. Ash-Saki, and S. Ghosh, “Resiliency Analysis and Improvement of Variational Quantum Factoring in Superconducting Qubit”, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020. [Acceptance Rate: 25%] Link
[C11] Alam, Mahabubul, A. Ash-Saki, and S. Ghosh, “An Efficient Circuit Compilation Flow for Quantum Approximate Optimization Algorithm”, IEEE Design Automation Conference (DAC), 2020. Link
[C10] Alam, Mahabubul, A. Ash-Saki, and S. Ghosh, “Accelerating Quantum Approximate Optimization Algorithm using Machine Learning”, IEEE Design Automation and Test in Europe (DATE), 2020. Link
[C9] Alam, Mahabubul, A. Ash-Saki, and S. Ghosh, “Design-Space Exploration of Quantum Approximate Optimization Algorithm under Noise”, IEEE Custom Integrated Circuit Conference (CICC), 2020. Link
[C8] A Ash-Saki, M Alam, S Ghosh, “Improving Reliability of True Random Number Generator using Machine Learning”, IEEE International Symposium on Quality Electronic Design (ISQED), 2020. Link
[C7] Li, J., M. Alam, A. Ash-Saki, S. Ghosh, “Hierarchical Improvement of Quantum Approximate Optimization Algorithm for Object Detection”, IEEE International Symposium on Quality Electronic Design (ISQED), 2020. Link
[C6] Qiu, L., M. Alam, A. Ash-Saki, and S. Ghosh, “Analyzing Resilience of Variational Quantum Factoring under Realistic Noise”, Govt Microcircuit Applications and Critical Technology (GOMACTECH), 2020. Link
[C5] A. Ash-Saki, Alam, Mahabubul, and S. Ghosh, “QURE: Qubit Re-allocation in Noisy Intermediate-scale Quantum Computers”, IEEE Design Automation Conference (DAC), 2019. Link
[C4] Bhattacharjee, D., A. Ash-Saki, M. Alam, A. Chattopadhyay, S. Ghosh, “MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers”, IEEE/ACM Intl Conf. On Computer Aided Design (ICCAD), 2019. Link
[C3] M. Alam, A. Ash-Saki, Swaroop Ghosh “ Addressing Temporal Variations in Qubit Quality Metrics for Parameterized Quantum Circuits”, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2019. [Acceptance Rate: xx%] Link
[C2] A. Ash-Saki, M. Alam, Swaroop Ghosh “True Random Number Generator using Superconducting Qubits”, IEEE Device Research Conference (DRC), 2019. [Acceptance Rate: NA] Link
[C1] A. Ash-Saki, M. Alam, Swaroop Ghosh “Decoherence Analysis of Multi-Depth and Multi-Qubit Quantum Circuits ”, Government Microcircuit Applications & Critical Technology Conference (Gomactech), 2019. [Acceptance Rate: NA] Link

Memory security [Sponsored by NSF]

Research

Next-generation memories such as, Spin-Transfer Torque RAM (STTRAM), Ferroelectric RAM (FeRAM), Resistive RAM (ReRAM), Phase Change RAM (PCRAM) and Domain Wall Memory (DWM) have brought lot of excitement in the design community due to leakage elimination, high density, non-volatility, low-power and high-speed. Significant research effort has been devoted to understand the viability of integrating NVMs across the memory hierarchy including Last Level Cache (LLC) and main memory. However, non-volatile memory (NVM) LLC brings new security challenges that were absent in their conventional volatile memory counterparts. The root cause is persistent data and the fundamental dependency of the NVM on ambient parameters such as, magnetic field and temperature that can be exploited for low-cost tampering. This project investigates the memory vulnerabilities, identifies new threat vectors and develops countermeasures.

Current students:

Rupshali Roy

Graduated students:

Karthikeyan Nagarajan, Sina Sayyah, Abdullah-Ash Saki, Asmit De, Nasim Imtiaz Khan, Rekha Govindraj, Anirudh Iyengar, Jae-won Jang, Navyata Gattu

Related publications

[BC1] Govindaraj, Rekha, Mohammad Nasim Imtiaz Khan and Swaroop Ghosh, “Spin Transfer Torque RAM and Domain Wall Memory Devices ”, In Security Opportunities in Nano Devices and Emerging Technologies, CRC Press, 2017. Link
[J12] Khan, N. I., De, A., & Ghosh, S. “Cache-Out: Leaking Cache Memory Using Hardware Trojan ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Accepted. [Impact factor: 1.94] Link
[J11] Chattopadhyay, A., Ghosh, S., Mukhopadhyay, D., & Burleson, W. “Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Accepted. [Impact factor: 1.94] Link
[J10] *Khan, M. N. I. & Ghosh, S. “Test Methodologies, and, Test Time Analysis and Compression for Emerging Non-Volatile Memory ”, IEEE Transactions on Reliability, 10, Accepted. [Impact factor: 2.73] Link
[J9] Govindaraj, Rekha, Swaroop Ghosh, and Srinivas Katkoori, “Design, Analysis and Application of Embedded Resistive RAM based Strong Arbiter PUF ”, IEEE Transactions on Dependable and Secure Computing, 2018. [Impact factor: 4.41] Link
[J8] Govindaraj, Rekha, Swaroop Ghosh, and Srinivas Katkoori, “CSRO-Based Reconfigurable True Random Number Generator Using RRAM ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018). [Impact factor: 1.744] Link
[J7] Khan, Mohammad Nasim Imtiaz, Anirudh S. Iyengar, and Swaroop Ghosh, “Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing of STTRAM ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018). [Impact factor: 1.744] Link
[J6] Motaman, Seyedhamidreza, Swaroop Ghosh, and Nitin Rathi, “Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM ”, IEEE Transactions on Emerging Topics in Computing (2017). [Impact factor: 3.626] Link
[J5] De, Asmit, Mohammad Nasim Imtiaz Khan, Jongsun Park, and Swaroop Ghosh, “Replacing eflash with sttram in iots: Security challenges and solutions ”, Journal of Hardware and Systems Security 1, no. 4 (2017): 328-339. [Impact factor: NA] Link
[J4] Swaroop Ghosh, “Spintronics and Security: Prospects, Vulnerabilities, Attack Models, and Preventions ”, Proceedings of the IEEE 104, no. 10 (2016): 1864-1893. [Impact factor: 9.107] Link
[J3] Iyengar, Anirudh, Swaroop Ghosh, and Srikant Srinivasan, “Retention Testing Methodology for STTRAM ”, IEEE Design & Test 33, no. 5 (2016): 7-15. [Impact factor: 1.538] Link
[J2] Anirudh Iyengar, Kenneth Ramclam, Swaroop Ghosh, Jae-Won Jang and Cheng-Wei Lin, “Spintronic PUFs for Security, Trust and Authentication”, ACM Journal of Emerging Topics Computing Systems (JETC Special Issue), 2016. [Impact factor: 0.82] Link
[J1] Anirudh Iyengar, Swaroop Ghosh and Kenneth Ramclam, “Domain wall magnet for embedded memory and hardware security”, Special Issue of Journal of Emerging Topics on Circuits and Systems (JETCAS Special Issue), 2015. [Impact factor: 1.52] Link
[C23] Karthikeyan Nagarajan, Mohammad Nasim Imtiaz Khan and Swaroop Ghosh “ ENTT: A Family of Emerging NVM-based Trojan Triggers ”, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019. [Acceptance Rate: 24%] Link
[C22] Mohammad Nasim Imtiaz Khan, Karthikeyan Nagarajan and Swaroop Ghosh “Hardware Trojans in Emerging Non-Volatile Memories”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019. [Acceptance Rate: 24%] Link
[C21] S. Ghosh, K.Nagarajan, S.Sayyah, N.Khan, A.Saki “(Invited Special Session Paper) Meeting the Conflicting Goals of Low-Power and Resiliency Using Emerging Memories”, IEEE International Online Testing Symposium (IOLTS), 2019. [Acceptance Rate: xx%] Link
[C20] Mohammad Nasim Imtiaz Khan and Swaroop Ghosh “ Analysis of Row Hammer Attack on STTRAM ”, IEEE 36th International Conference on Computer Design (ICCD), 2018. [Acceptance Rate: 29%]  Link
[C19] Mohammad Nasim Imtiaz Khan and Swaroop Ghosh “ Test of Supply Noise for Emerging Non-Volatile Memory ”, IEEE 49th International Test Conference (ITC), 2018. [Acceptance Rate: xx%]  Link
[C18] Mohammad Nasim Imtiaz Khan and Swaroop Ghosh “ Information Leakage Attacks on Emerging Non-Volatile Memory and Countermeasures ”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2018. [Acceptance Rate: 25%] Link
[C17] Mohammad Nasim Imtiaz Khan and Swaroop Ghosh “ Fault Injection Attacks on Emerging Non-Volatile Memory and Countermeasures ”, Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP), 2018. [Acceptance Rate:] Link
[C16] Asmit De, Anirudh Iyengar, Mohammad Nasim I Khan, Sung-Hao Lin, Sandeep Thirumala, Swaroop Ghosh and Sumeet Gupta “ CTCG: Charge-trap based camouflaged gates for reverse engineering prevention ”, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018. [Acceptance Rate:20.2%] Link
[C15] Mohammad Nasim Imtiaz Khan and Swaroop Ghosh “ Test challenges and solutions for emerging non-volatile memories ”, IEEE 36th VLSI Test Symposium (VTS), 2018. [Acceptance Rate:] Link
[C14] Seyedhamidreza Motaman, Mohammad Nasim Imtiaz Khan and Swaroop Ghosh “ Novel application of spintronics in computing, sensing, storage and cybersecurity ”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018. [Acceptance Rate:] Link
[C13] Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Alex Yuan, Anupam Chattopadhyay, Swaroop Ghosh “ Side-channel attack on sttram based cache for cryptographic application ”, IEEE 35th International Conference on Computer Design (ICCD), 2017. [Acceptance Rate:] Link
[C12] Mohammad Nasim Imtiaz Khan, Anirudh S Iyengar and Swaroop Ghosh “ Novel magnetic burn-in for retention testing of STTRAM ”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. [Acceptance Rate:] Link
[C11] Radha Krishna Aluru and Swaroop Ghosh “ Novel magnetic burn-in for retention testing of STTRAM ”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. [Acceptance Rate:] Link
[C10] Alexander Holst, Jae-Won Jang, Swaroop Ghosh “ Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access Memory ”, 18th International Symposium on Quality Electronic Design (ISQED), 2017. [Acceptance Rate:] Link
[C9] Swaroop Ghosh, Mohammad Nasim Imtiaz Khan, Asmit De and Jae-Won Jang, “ Security and privacy threats to on-chip Non-Volatile Memories and countermeasures ”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016. [Acceptance Rate: xx %] Link
[C8] Rekha Govindaraj and Swaroop Ghosh, “ A strong arbiter PUF using resistive RAM within 1T-1R memory architecture ”, IEEE 34th International Conference on Computer Design (ICCD), 2016. [Acceptance Rate: xx %] Link
[C7] Anirudh Iyengar, Swaroop Ghosh, Nitin Rathi and Helia Naeimi, “ Side channel attacks on STTRAM and low-overhead countermeasures ”, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016. [Acceptance Rate: xx %] Link
[C6] Jae-Won Jang and Swaroop Ghosh, “ Performance impact of magnetic and thermal attack on STTRAM and low-overhead mitigation techniques ”, ACM International Symposium on Low Power Electronics and Design (ISLPED), 2016. [Acceptance Rate: xx %] Link
[C5] Nitin Rathi, Swaroop Ghosh Anirudh Iyengar and Helia Naeimi, “Data privacy in non-volatile cache: Challenges, attack models and solutions”, Asis and South Pacific Design Automation Conference (ASP-DAC), 2016. Link
[C4] Swaroop Ghosh and Rekha Govindaraj, “Spintronics for associative computation and hardware security”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2015. Link
[C3] Jae-Won Jang, Jongsun Park, Swaroop Ghosh and Swarup Bhunia, “Self-correcting STTRAM under magnetic field attacks”, Design Automation Conference (DAC), 2015. Link
[C2] Jae-Won Jang and Swaroop Ghosh, “Design and analysis of novel SRAM PUFs with embedded latch for robustness”, IEEE International Symposium on Quality Electronic Design (ISQED), 2015. Link
[C1] Anirudh Iyengar, Kenneth Ramclam and Swaroop Ghosh, “DWM-PUF: A low-overhead, memory-based security primitive”, IEEE Hardware Oriented Security and Trust (HOST), 2014. Link

Hardware and system security [Sponsored by DARPA YFA (completed)]

Research

Semiconductor supply chain is exposed to untrusted third parties during design, manufacturing, assembly and test. Therefore, hardware cannot be considered as root-of-trust anymore. Numerous hardware-assisted attacks spanning the entire computing stack are now possible. This research explores hardware security threats such as, side channel attack, tampering/Trojan insertion, reverse engineering and recycling and develops various countermeasures such as, obfuscation, tamper/recycling sensors and PUFs. We also study the prospects of accelerating system security threats such as, buffer overflow and return-oriented programming using hardware security primtives.

Graduated students:

Md. Mahabubul Alam, Abdullah-Ash Saki, Navyata Gattu, Asmit De, Nasim Imtiaz Khan, Rekha Govindraj, Anirudh Iyengar, Jae-won Jang, Deepak Reddy Vontela, Ithihasa Reddy Nirmala

Related publications

[J1] Swaroop Ghosh, Abhishek Basak and Swarup Bhunia, “How Secure Are Printed Circuit Boards Against Trojan Attacks?”, IEEE Design & Test, 2015. [Impact factor: 1.14] Link
[C9] Asmit De and Swaroop Ghosh, “HeapSafe: Securing Unprotected Heaps in RISC-V ”, IEEE VLSI Design, 2022. [Acceptance Rate: NA%]  Link
[C8] Gattu, Navyata, Khan, M. N. I., De, A. and S. Ghosh, “Power side channel attack analysis and detection”, IEEE International Conference on Computer Aided Design (ICCAD), 2020. [Acceptance Rate: 24%] Link
[C7] Asmit De and Swaroop Ghosh, “Preventing Reverse Engineering using threshold voltage defined multi-input camouflaged gates”, IEEE International Symposium on Technologies for Homeland Security (HST), 2017. Link
[C6] Ithihasa Reddy Nirmala, Deepak Reddy Vontela, Swaroop Ghosh and Anirudh Iyengar, “A novel threshold voltage defined switch for circuit camouflaging”, IEEE European Test Symposium (ETS), 2016. Link
[C5] Deepak Reddy Vontela and Swaroop Ghosh, “Methodologies to exploit ATPG tools for de-camouflaging”, IEEE International Symposium on Quality Electronic Design (ISQED), 2017. Link
[C4] Deepakreddy Vontela and Swaroop Ghosh, “Methodologies to exploit ATPG tools for de-camouflaging”, IEEE International Symposium on Quality Electronic Design (ISQED), 2017. Link
[C3] Anirudh Iyengar and Swaroop Ghosh, “Threshold Voltage Defined Switches for Programmable Gates”, Government Microcircuit Applications and Critical Technology (Gomactech), 2016. Link
[C2] Cheng-Wei Lin and Swaroop Ghosh, “A family of Schmitt-Trigger-based arbiter-PUFs and selective challenge-pruning for robustness and quality”, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2015. Link
[C1] Cheng-Wei Lin, Jae-Won Jang and Swaroop Ghosh, “Schmitt-Trigger-based Recycling Sensor and Robust and High-Quality PUFs for Counterfeit IC Detection”, Government Microcircuit Applications and Critical Technology (Gomactech), 2015. Link

Intelligent memories [Sponsored by SRC/Intel, NSF]

Research

Memory and processing units have been improved asymmetrically in terms of performance/energy consumption due to the transistor scaling. Faster processing units require frequent data from memory (which remains slow). Furthermore, the system energy consumption is dominated by energy-intensive data-transfers (Von-Neumann bottleneck). In big data era, Von-Neumann bottleneck makes the architecture platform incapable of meeting the real-time data processing requirements. This project explores compute-capable intelligent memories to eliminate Von-Neumann bottleneck and enhance the system performance and energy-efficiency. We consider wide range of data-intensive applications including numerical calculations, post-quantum cryptography, hashing and so on.

Graduated students:

Sina Sayyah, Karthik Nagarajan, Asmit De, Md. Mahabubul Alam, Abdullah-Ash SakiNasim Imtiaz Khan, Rekha Govindraj, Anirudh Iyengar, Jae-won Jang, Deepak Reddy Vontela, Ithihasa Reddy Nirmala

Related publications

[J14] Ensan, S. & Ghosh, S. “ReLOPE: Resistive RAM based Linear First Order Partial Differential Equation Solver ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020. Accepted. [Impact factor: 1.94] Link
[J13] Chung, J., Choi, W., Park, J., & Ghosh, S. “Domain Wall Memory based Design of Deep Neural Network Convolutional Layers ”, IEEE Access. Accepted. [Impact factor: 4.098] Link
[J12] Abdullah-Ash Saki, Nasim Imtiaz Khan, Swaroop Ghosh “Reconfigurable and Dense Analog Circuit Design using Two Terminal Resistive Memory ”, IEEE Transactions on Emerging Topics in Computing. Accepted. [Impact factor: 3.626] Link
[J11] Dongyeob Shin; Wonseok Choi; Jongsun Park; Swaroop Ghosh “Sensitivity based Error Resilient Techniques with Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators ”, Special Issue (on IEEE/IBM AI Compute Symposium) of IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Accepted. [Impact factor: 3.433] Link
[J10] *Seyedhamidreza Motaman, Ghosh, Swaroop, Jongsun Park “A Perspective on Test Methodologies for Supervised Machine Learning Accelerators ”, Special Issue (on IEEE/IBM AI Compute Symposium) of IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Accepted. [Impact factor: 3.433] Link
[J9] *Saki, A. A., *Lin, S. H., *Alam, M., Ghosh, S., Thirumala, S.K & S. Gupta “A Family of Compact Non-Volatile Flip-Flops with Ferroelectric FET ”, IEEE Trans. on Circuits and Systems-1, 11. Accepted. [Impact factor: 2.83] Link
[J8] Rangachar Srinivasa, Srivatsa, Ramanathan, Akshay Krishna, Li, Xueqing, Chen, Wei-Hao, Gupta, Sumeet, Chang, Meng-Fan, Ghosh, Swaroop, Sampson, John and Narayanan, Vijaykrishnan “ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support ”, IEEE Transactions on Circuits and Systems I: Regular Papers, Accepted. [Impact factor: 2.823] Link
[J7] Motaman, Seyedhamidreza, Swaroop Ghosh, and Jaydeep Kulkarni, “Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing ”, ACM Journal on Emerging Technologies in Computing Systems (JETC) 14, no. 1 (2018): 8. [Impact factor: NA] Link
[J6] Ghosh, Swaroop, Rashmi Jha, Anirudh Iyengar, and Rekha Govindaraj, “Design Space Exploration for Selector Diode-STTRAM Crossbar Arrays ”, IEEE Transactions on Magnetics 54, no. 6 (2018): 1-5. [Impact factor: 1.467] Link
[J5] Syedhamidreza Motaman and Swaroop Ghosh, “Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016. [Impact factor: 1.142] Link
[J4] Jinil Chung, Kenneth Ramclam, Jongsun Park and Swaroop Ghosh, “Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design”, IEEE Transactions on Circuits and Systems-I, 2015. [Impact factor: 2.4] Link
[J3] Anirudh Iyengar, Swaroop Ghosh and Jae-Won Jang, “MTJ-based State Retentive Flip-Flop with Enhanced-Scan Capability to Sustain Sudden Power Failure”, IEEE Transactions on Circuits and Systems-I, 2015. [Impact factor: 2.4] Link
[J2] Robert Karam, Ruchir Puri, Swaroop Ghosh and Swarup Bhunia, “Emerging Trends in Design and Applications of Memory based Computing and Content Addressable Memories”, Proceedings of the IEEE (Special Issue), 2015. [Impact factor: 5.5] Link
[J1] Syedhamidreza Motaman, Anirudh Iyengar and Swaroop Ghosh, “Domain Wall Memory-Layout, Circuit and Synergistic Systems”, IEEE Transactions on Nanotechnology, 2015. [Impact factor: 1.62] Link
[C14] Karthikeyan Nagarajan, Sina Sayyah Ensan, Swagata Mandal, Anupam Chattopadhyay, Swaroop Ghosh “(Invited Special Session Paper) iMACE: In-Memory Acceleration of Classic McEliece Encoder”, IEEE International Symposium on VLSI (ISVLSI), 2019. [Acceptance Rate: xx%] Link
[C13] Seyedhamidreza Motaman and Swaroop Ghosh. “ Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays ”, IEEE 36th International Conference on Computer Design (ICCD), 2018. [Acceptance Rate: 29%]  Link
[C12] Srivatsa Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei-Hao Chen, Fu-Kuo Hsueh, Chih-Chao Yang, Chang-Hong Shen, Jia-Min Shieh, Sumeet Gupta, Meng-Fan Marvin Chang, Swaroop Ghosh, Jack Sampson and Vijaykrishnan Narayanan “ A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support (ISLPED) ”, Proceedings of the International Symposium on Low Power Electronics and Design, 2018. [Acceptance Rate: 25%] Link
[C11] Jinil Chung, Jongsun Park and Swaroop Ghosh, “ Domain wall memory based convolutional neural networks for bit-width extendability and energy-efficiency ”, ACM International Symposium on Low Power Electronics and Design (ISLPED), 2016. [Acceptance Rate: xx %] Link
[C10] Swaroop Ghosh and Rekha Govindaraj, “ Domain wall memory based convolutional neural networks for bit-width extendability and energy-efficiency ”, IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016. [Acceptance Rate: xx %] Link
[C9] Rekha Govindaraj and Swaroop Ghosh, “Design and analysis of 6-T 2-MTJ ternary Content Addressable Memory”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015. Link
[C8] Seyedhamidreza Motaman, Swaroop Ghosh and Jaydeep P. Kulkarni, “A novel slope detection technique for robust STTRAM sensing”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015. Link
[C7] Jinil Chung, Kenneth Ramclam, Jongsun Park and Swaroop Ghosh, “Domain Wall Memory based Digital Signal processors for area and energy-efficiency”, Design Automation Conference (DAC), 2015. Link
[C6] Syedhamidreza Motaman, Swaroop Ghosh and Nitin Rathi, “Impact of process-variations in STTRAM and adaptive boosting for robustness”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015. Link
[C5] Syedhamidreza Motaman, Anirudh Iyengar and Swaroop Ghosh, “Synergistic circuit and system design for energy-efficient and robust domain wall caches”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2014. Link
[C4] Anirudh Iyengar and Swaroop Ghosh, “Modeling and analysis of domain wall dynamics for robust and low-power embedded memory”, Design Automation Conference (DAC), 2014. Link
[C3] Syedhamidreza Motaman and Swaroop Ghosh, “Simultaneous sizing, reference voltage and clamp voltage biasing for robustness, self-calibration and testability of STTRAM arrays”, Design Automation Conference (DAC), 2014. Link
[C2] Swaroop Ghosh, “Design methodologies for high density domain wall memory”, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2013. Link
[C1] Swaroop Ghosh, “Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5Watts of power”, Design Automation Conference (DAC), 2013. Link